FIG. 14 is a block diagram illustrating a configuration of a conventional digital still camera.
In this digital camera, when a user operates a camera operation switch 201 (consists of a main switch, a release switch, etc. in a camera), a total control CPU 200 detects a state change of the camera operation switch 201, and supplies power to respective circuit blocks.
An image of an object within an imaging area is formed on an image sensing device 204 through main image sensing optical systems 202 and 203, and is converted into an analog electric signal. The analog electric signal from the image sensing device 204 is processed by a CDS/AGC circuit 205, then sequentially converted into a digital signal in an A/D converter 206 pixel by pixel.
A driver circuit 207 controls the horizontal and vertical operation of the image sensing device 204 on the basis of a signal from a timing generator 208 which determines the entire operation timing, thereby an image sensing device 204 outputs an image signal.
Similarly, the CDS/AGC circuit 205 and the A/D converter 206 also operate on the basis of the timing signal provided by the timing generator 208.
Reference numeral 209 denotes a selector that selects a signal on the basis of a signal from the CPU 200. An output from the A/D converter 206 is inputted into a memory controller 215 through a selector 209, and all signal outputs are transmitted to a frame memory 216. Therefore, since all the pixel data of every image sensing frame are temporarily stored in the frame memory 216 in this case, all the pixel data of photographed images are written in the frame memory 216 in continuous shooting and the like.
After writing into the frame memory 216, by the control of the memory controller 215, the contents of the frame memory 216 storing pixel data are transmitted to a camera digital signal processing unit (DSP) 210 through the selector 209. In the camera DSP 210, R, G and B signals are generated based on each pixel data of each image stored in the frame memory 216.
Usually, before image sensing, a monitor display 212 performs finder display etc. by periodically transmitting the generated R, G and B signals to video memory 211 (every frame).
When a user directs recording of an image by operating the camera operation switch 201, each pixel data for one frame is read from the frame memory 216 in response to a control signal from the CPU 200, and after performing image processing in the camera DSP 210, each pixel data is temporarily stored in work memory 213.
Then, the data in the work memory 213 is compressed in a compression/decompression section 214 on the basis of a predetermined compression format, and the compressed data is stored in external nonvolatile memory (or external memory) 217. Usually, nonvolatile memory such as flash memory is used as the external nonvolatile memory 217.
Further, when observing photographed image data, data that is compressed and stored in the external memory 217 is decompressed to the normal data of every pixel by the compression/decompression section 214. A photographed picture is displayed on the monitor display 212 by transmitting the decompressed data of every pixel to the video memory 211.
Thus, a usual digital camera has such structure that an output from the image sensing device 204 is converted into image data through a signal processing circuit at almost real time, and the result is outputted to memory or a monitor circuit.
In a digital camera system like the above, in order to improve performance, such as continuous shooting (for example, to achieve a rate of 10 frames/sec), it is necessary to improve the system itself, including an image sensing device, such as to increase reading speed from the image sensing device and to increase writing speed of data from image sensing device into frame memory etc.
As one of improvement methods therefor, as shown in FIG. 15, known is a two-output type device in which a horizontal CCD, which is an image sensing device, is divided into two regions, and signals are outputted by each region. FIG. 15 briefly shows the structure of a two-output type CCD device. In the CCD shown in FIG. 15, charges of the respective pixels generated in photo diode sections 190 are transmitted to vertical CCDs 191 all at once at certain predetermined timing. Then, the charges in the vertical CCDs 191 of one horizontal line are transmitted to the horizontal CCDs 192 and 193 at the next timing.
In the structure shown in FIG. 15, the horizontal CCD 192 transmits the charges toward an amplifier 194 on the left-hand side at every transfer clock. Further, the horizontal CCD 193 transmits the charges toward an amplifier 195 on the right-hand side at every transfer clock. Thus, the image data of this CCD is read out in such a manner that the image is divided into right and left areas bordering on the center of a screen.
Usually, the amplifiers 194 and 195 are formed within a CCD device. Nevertheless, since they are considerably apart from each other in layout, the relative characteristics of both amplifiers 194 and 195 do not necessarily completely coincide. For this reason, signal levels of the right and left outputs are matched by adjusting external adjusting sections 197 and 199 when the outputs from the amplifiers 194 and 195 are processed by separate CDS/AGC circuits 196 and 198, respectively.
As described above, a method for simultaneously reading signals from a plurality of output channels to realize an image sensing device capable of performing high-speed readout is indispensable technology so as to bring future digital cameras further close to silver halide cameras. Note, products with the specification of 8 frames/sec have already realized in silver halide cameras of a single-lens reflex type.
However, although a plurality of output channels are advantageous in speed, the plurality of output channels are apparently disadvantageous, in comparison with a one-output channel, in the matching property of output levels.
With a simple manually adjusting method such as analog adjustment in a conventional CDS/AGC circuit section, and digital adjustment which adjusts output levels of both channels to match each other after A/D conversion, even if the adjustment is closely made in manufacturing processes, a value of, e.g., a volume (VR) resistor changes in according with environmental conditions. Further, the possibility that temperature characteristics of the two CDS/AGC circuits perfectly coincides with each other is very rare.
Usually, if the relative precision between the right and left output channels exceeds ±1% when such a method of reading an image sensing device is performed, the imbalance of their boundary is clearly seen on a screen.